Method for reducing execution jitter in multi-core processors within an information handling system

ABSTRACT

A method of reducing execution jitter includes a processor having several cores and control logic that receives core configuration parameters. Control logic determines if a first set of cores are selected to be disabled. If none of the cores is selected to be disabled, the control logic determines if a second set of cores is selected to be jitter controlled. If the second set of cores is selected to be jitter controlled, the second set of cores is set to a first operating state. If the first set of cores is selected to be disabled, the control logic determines a second operating state for a third set of enabled cores. The control logic determines if the third set of enabled cores is jitter controlled, and if the third set of enabled cores is jitter controlled, the control logic sets the third set of enabled cores to the second operating state.

This application is a reissue of, and claims the benefit of the filingdate of, U.S. patent application Ser. No. 13/652,512, filed on Oct. 16,2012, now U.S. Pat. No. 9,081,625, titled “METHOD FOR REDUCING EXECUTIONJITTER IN MULTI-CORE PROCESSORS WITHIN AN INFORMATION HANDLING SYSTEM,”the disclosure of which is hereby incorporated by reference herein inits entirety.

BACKGROUND

1. Technical Field

The present disclosure generally relates to operation of multi-coreprocessors within an information handling system and in particular toreducing execution jitter in multi-core processors within an informationhandling system.

2. Description of the Related Art

As the value and use of information continue to increase, individualsand businesses seek additional ways to process and store information.One option available to users is information handling systems. Aninformation handling system generally processes, compiles, stores,and/or communicates information or data for business, personal, or otherpurposes, thereby allowing users to take advantage of the value of theinformation. Because technology and information handling needs andrequirements vary between different users or applications, informationhandling systems may also vary regarding what information is handled,how the information is handled, how much information is processed,stored, or communicated, and how quickly and efficiently the informationmay be processed, stored, or communicated. The variations in informationhandling systems allow for information handling systems to be general orconfigured for a specific user or specific use such as financialtransaction processing, airline reservations, enterprise data storage,or global communications. In addition, information handling systems mayinclude a variety of hardware and software components that may beconfigured to process, store, and communicate information and mayinclude one or more computer systems, data storage systems, andnetworking systems.

The information handling system can be designed with one or moremulti-core processors. A multi-core processor is a single computingcomponent with two or more independent central processing units,processor cores, or cores that are able to read and execute programinstructions or software code. The program instructions or software codecan be regular computer instructions. The multiple cores can runmultiple instructions at the same time, increasing the overallprocessing speed for programs. The multiple cores typically areintegrated onto a single integrated circuit die or integrated circuit oronto multiple dies in a single chip package.

As processors with multiple cores implement higher and dynamic frequencyranges, these changes can result in non-deterministic code executiontiming. Some software applications require very specific ordeterministic code execution timing. Examples of these applicationsinclude real time applications, financial trading applications, andcontrol applications. It is desirable for these applications to havepredictable execution times. Execution jitter is defined as thedifference in execution time for a given program or thread between thepredicted execution time and the actual execution time at a givenfrequency. For example, if a given thread is predicted to execute in 10milliseconds and some measured execution times are 8, 9, 11 and 13milliseconds, the execution jitter is the difference between themeasured times and 10 milliseconds. Execution jitter can occur forthreads that execute in either longer or shorter times than thepredicted or desired execution times. In order to control the level ofexecution jitter within an acceptable range, the multiple cores areforced to operate at the lowest operating frequency or lowestperformance level. A method for reducing execution jitter in softwareprograms running on multi-core processors is therefore needed.

BRIEF SUMMARY

Disclosed is a method for reducing execution jitter in a processingenvironment that includes a processor having several cores and controllogic that receives core configuration data. The control logicdetermines if a first set of cores are to be disabled. If none of thefirst set of cores are to be disabled, the control logic determines if asecond set of cores are to be jitter controlled. If the second set ofcores are to be jitter controlled, the second set of cores are set to afirst operating state. If the first set of cores are to be disabled, thefirst set of cores are disabled based upon physical location, and thecontrol logic determines a second operating state for a third set of oneor more enabled cores. The control logic determines if the third set ofenabled cores are to be jitter controlled, and if the third set ofenabled cores are jitter controlled, the control logic sets the thirdset of enabled cores to the second operating state determined by thenumber of disabled cores. The method provides consistent execution timesfor threads running on multiple cores.

A multi-core processor is disclosed that includes a plurality of coresin communication with control logic having firmware executing thereon.The firmware configures the control logic to receive at least one coreconfiguration parameter and to determine from the at least oneconfiguration parameter if a first set of one or more cores is selectedto be disabled. In response to none of the first set of cores selectedto be disabled, the control logic determines if a second set of one ormore cores is selected to be jitter controlled. In response to thesecond set of the cores being selected to be jitter controlled, thecontrol logic sets the second set of cores to a first operating statethat reduces jitter. In response to the first set of cores beingselected to be disabled, the control logic disables the first set ofcores and determines a second operating state that reduces jitter for athird set of one or more enabled cores that are enabled for turbo stateoperation. The control logic determines if the third set of enabledcores are selected to be jitter controlled and, in response to the thirdset of enabled cores selected to be jitter controlled, the control logicsets the third set of enabled cores to the second operating state thatreduces jitter.

Also disclosed is an information handling system (IHS) that comprises aprocessor having a plurality of cores and control logic. A memory iscoupled to the processor via a system interconnect. The control logichas firmware executing thereon to reduce execution jitter. The firmwareconfigures the control logic to determine if a first set of cores are tobe disabled, and in response to none of the cores being selected fordisabling, the control logic determines if a second set of cores are tobe jitter controlled. In response to the second set of the cores beingjitter controlled, the control logic sets the second set of cores to afirst operating state. In response to the first set of cores beingselected for disabling, the first set of cores are disabled based uponphysical location, and the control logic determines a second operatingstate for a third set of one or more enabled cores that are enabled forturbo state operation. The control logic determines if the third set ofenabled cores are to be jitter controlled; and in response to the thirdset of enabled cores being jitter controlled, the third set of enabledcores are set to the second operating state determined by the number ofdisabled cores. The information handling system provides consistentexecution times for threads running on multiple cores.

The above summary contains simplifications, generalizations andomissions of detail and is not intended as a comprehensive descriptionof the claimed subject matter but, rather, is intended to provide abrief overview of some of the functionality associated therewith. Othersystems, methods, functionality, features and advantages of the claimedsubject matter will be or will become apparent to one with skill in theart upon examination of the following figures and detailed writtendescription.

BRIEF DESCRIPTION OF THE DRAWINGS

The description of the illustrative embodiments can be read inconjunction with the accompanying figures. It will be appreciated thatfor simplicity and clarity of illustration, elements illustrated in thefigures have not necessarily been drawn to scale. For example, thedimensions of some of the elements are exaggerated relative to otherelements. Embodiments incorporating teachings of the present disclosureare shown and described with respect to the figures presented herein, inwhich:

FIG. 1 illustrates an example information handling system within whichvarious aspects of the disclosure can be implemented, according to oneor more embodiments;

FIG. 2 illustrates an example of core configuration parameters beingtransmitted from the basic input output system (BIOS) to the processorcontrol logic in accordance with one or more embodiments;

FIG. 3 is a flow chart illustrating one example of the method by whichcores are disabled and/or enabled for (a) operation and (b) jittercontrol, according to one or more embodiments;

FIG. 4 is a flow chart illustrating one example of the method by whichcores are disabled, according to one or more embodiments;

FIG. 5 is a flow chart illustrating one example of the method by whichan ordered lookup table is generated, according to one or moreembodiments; and

FIG. 6 is an example ordered lookup table identifying the sequence ofenabling the cores based on the total number of enabled cores, accordingto one embodiment.

DETAILED DESCRIPTION

The illustrative embodiments provide an information handling system(IHS), a multi-core processor and a method performed within theinformation handling system for (1) reducing execution jitter inmulti-core processors, (2) enabling one or more processor cores within amulti-core processor to operate at a pre-determined frequency and (3)providing consistent execution times for threads running on multiplecores within a multi-core processor.

In the following detailed description of exemplary embodiments of thedisclosure, specific exemplary embodiments in which the disclosure maybe practiced are described in sufficient detail to enable those skilledin the art to practice the disclosed embodiments. For example, specificdetails such as specific method orders, structures, elements, andconnections have been presented herein. However, it is to be understoodthat the specific details presented need not be utilized to practiceembodiments of the present disclosure. It is also to be understood thatother embodiments may be utilized and that logical, architectural,programmatic, mechanical, electrical and other changes may be madewithout departing from general scope of the disclosure. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present disclosure is defined by the appendedclaims and equivalents thereof.

References within the specification to “one embodiment,” “anembodiment,” “embodiments”, or “one or more embodiments” are intended toindicate that a particular feature, structure, or characteristicdescribed in connection with the embodiment is included in at least oneembodiment of the present disclosure. The appearance of such phrases invarious places within the specification are not necessarily allreferring to the same embodiment, nor are separate or alternativeembodiments mutually exclusive of other embodiments. Further, variousfeatures are described which may be exhibited by some embodiments andnot by others. Similarly, various requirements are described which maybe requirements for some embodiments but not other embodiments.

It is understood that the use of specific component, device and/orparameter names and/or corresponding acronyms thereof, such as those ofthe executing utility, logic, and/or firmware described herein, are forexample only and not meant to imply any limitations on the describedembodiments. The embodiments may thus be described with differentnomenclature and/or terminology utilized to describe the components,devices, parameters, methods and/or functions herein, withoutlimitation. References to any specific protocol or proprietary name indescribing one or more elements, features or concepts of the embodimentsare provided solely as examples of one implementation, and suchreferences do not limit the extension of the claimed embodiments toembodiments in which different element, feature, protocol, or conceptnames are utilized. Thus, each term utilized herein is to be given itsbroadest interpretation given the context in which that terms isutilized.

FIG. 1 illustrates a block diagram representation of an exampleinformation handling system (IHS) 100, within which one or more of thedescribed features of the various embodiments of the disclosure can beimplemented. For purposes of this disclosure, an information handlingsystem, such as IHS 100, may include any instrumentality or aggregate ofinstrumentalities operable to compute, classify, process, transmit,receive, retrieve, originate, switch, store, display, manifest, detect,record, reproduce, handle, or utilize any form of information,intelligence, or data for business, scientific, control, or otherpurposes. For example, an information handling system may be a handhelddevice, personal computer, a server, a network storage device, or anyother suitable device and may vary in size, shape, performance,functionality, and price. The information handling system may includerandom access memory (RAM), one or more processing resources such as acentral processing unit (CPU) or hardware or software control logic,ROM, and/or other types of nonvolatile memory. Additional components ofthe information handling system may include one or more disk drives, oneor more network ports for communicating with external devices as well asvarious input and output (I/O) devices, such as a keyboard, a mouse, anda video display. The information handling system may also include one ormore buses operable to transmit communications between the varioushardware components.

Referring specifically to FIG. 1 , example IHS 100 includes one or moreprocessor(s) 102 coupled to system memory 130 via system interconnect115. System interconnect 115 can be interchangeably referred to as asystem bus, in one or more embodiments. System memory 130 can includetherein a plurality of software and/or firmware modules includingfirmware (F/W) 132, basic input/output system (BIOS) 134, operatingsystem (O/S) 136, and application(s) 138. The one or more softwareand/or firmware modules within system memory 130 can be loaded intoprocessor(s) 102 during operation of IHS 100.

Processor(s) 102 include several processor cores, including core 0 104,core 1 106, core 2 108, core 3 110, core 4 112, core 5 114, core 6 116and core 7 118. Cores 104-118 can communicate with each other and withcontrol logic 120. Control logic 120 can control the operation of cores104-118. According to one aspect of the described embodiments, controllogic 120 can control the operating frequency and voltage or operatingstate of cores 104-118. Control logic 120 can also receive softwareand/or firmware modules from system memory 130 during the operation ofprocessor(s) 102. In one embodiment, clock 121 is provided onprocessor(s) 102 and enables the generation of several differentperiodic frequency signals that can be applied to one or more of thecores 104-118 within processor(s) 102.

IHS 100 further includes one or more input/output (I/O) controllers 140which support connection by, and processing of signals from, one or moreconnected input device(s) 142, such as a keyboard, mouse, touch screen,or microphone. I/O controllers 140 also support connection to andforwarding of output signals to one or more connected output devices144, such as a monitor or display device or audio speaker(s).Additionally, in one or more embodiments, one or more device interfaces146, such as an optical reader, a universal serial bus (USB), a cardreader, Personal Computer Memory Card International Association (PCMCIA)slot, and/or a high-definition multimedia interface (HDMI), can beassociated with IHS 100. Device interface(s) 146 can be utilized toenable data to be read from or stored to corresponding removable storagedevice(s) 148, such as a compact disk (CD), digital video disk (DVD),flash drive, or flash memory card. Device interfaces 146 can furtherinclude General Purpose I/O interfaces such as I²C, SMBus, andperipheral component interconnect (PCI) buses.

IHS 100 comprises a network interface device (NID) 150. NID 150 enablesIHS 100 to communicate and/or interface with other devices, services,and components that are located external to IHS 100. These devices,services, and components can interface with IHS 100 via an externalnetwork, such as example network 160, using one or more communicationprotocols. Network 160 can be a local area network, wide area network,personal area network, and the like, and the connection to and/orbetween network and IHS 100 can be wired or wireless or a combinationthereof. For purposes of discussion, network 160 is indicated as asingle collective component for simplicity. However, it is appreciatedthat network 160 can comprise one or more direct connections to otherdevices as well as a more complex set of interconnections as can existwithin a wide area network, such as the Internet.

Those of ordinary skill in the art will appreciate that the hardwarecomponents and basic configuration depicted in FIG. 1 and describedherein may vary. For example, the illustrative components within IHS 100are not intended to be exhaustive, but rather are representative tohighlight components that can be utilized to implement aspects of thepresent disclosure. For example, other devices/components may be used inaddition to or in place of the hardware depicted. The depicted exampledoes not convey or imply any architectural or other limitations withrespect to the presently described embodiments and/or the generaldisclosure.

With reference now to FIG. 2 , there is illustrated one embodiment ofcore configuration parameters 210 being transmitted from the basic inputoutput system (BIOS) 134 to the processor control logic 120. In thediscussion of FIG. 2 , reference is also made to components illustratedin FIG. 1 . During the initial startup of IHS 100 and processor(s) 102,core configuration parameters 210 are transmitted from the BIOS 134 tothe processor control logic 120. The core configuration parameters 210include operating states 212 for the cores 104-118. According to oneaspect of the disclosure, examples of these operating states 212 include(a) identification of one or more cores selected to be enabled foroperation at frequencies equal to or higher than the minimum clockfrequency or core operating frequency and (b) an identification ofspecific cores selected to be disabled, such that the disabled cores arenot operational. The operating states 212 identifies which of the one ormore of cores 104-118 are to be selected to be disabled and/or enabledand identifies which of the one or more cores 104-118 are to becontrolled for execution jitter. Operating frequencies that are higherthan the minimum core operating frequency are referred to as turbostates. For example, if the normal or minimum core operating frequencyis 2.0 GHz, operating states 212 can be set or pre-determined by a usersuch that one or more cores 104-118 operate at higher core frequenciessuch as 2.5 GHz, 3.0 GHz, 3.5 GHz, 4.0 GHz or other frequencies. Themaximum core frequency is subject to on-chip limits in temperature,current, and power consumption. In one or more embodiments, the coreconfiguration parameters 210 also include an ordered lookup table 214 ofthe cores, in which the cores are ordered by the maximum physicaldistance separating each core on the chip or die. For example, as shownin FIG. 1 , core 0 104 is physically located further away from core 7118 than from core 4 112. Ordered lookup table 214 is used to select oneor more cores 104-118 for operation.

The core configuration parameters 210 can be pre-determined by a userand stored in (BIOS) 134. For example, operating states 212 can directfour of the cores 104-118 (e.g., core 0-core 3) to be disabled fromoperating and another (i.e., different) four of the cores 104-118 (e.g.,core 4-core 7) to be enabled for operation and thus operate at a highercore operating frequency.

FIG. 3 illustrates a flowchart of exemplary methods by which cores are(a) disabled and enabled for operation and by which (b) cores arecontrolled for reducing execution jitter. Generally, method 300represents a computer-implemented method to reduce execution jitter inmulti-core processors and to enable cores to be operated at higheroperating frequencies. In the discussion of FIG. 3 , reference is alsomade to components illustrated in FIG. 1 and FIG. 2 . According to oneaspect of the disclosure, disabled cores do not perform execution ofinstructions and do not generate heat, while enabled cores operate at ahigher frequency that is variable depending upon processor workloads andother factors that are internal to and based on the design of theprocessors. Jitter controlled cores are set to a pre-determined clockfrequency as can be specified by a user. And, different jittercontrolled cores can have different clock frequencies.

Method 300 begins at the start block and proceeds to block 302 at whichcontrol logic 120 determines if any of the cores 104-118 are to bedisabled from operation. Disabled cores are identified through the useof core configuration parameters 210 received from BIOS 134. Disabledcores do not operate and thus do not execute any instructions. Accordingto one embodiment, the minimum core operating frequency is the defaultor reference operating frequency for the cores. In response to none ofthe cores 104-118 being selected to be disabled, control logic 120determines if any of cores 104-118 are to be jitter controlled (block308). In response to none of the cores 104-118 being selected to bejitter controlled, method 300 ends. In response to one or more of thecores 104-118 being selected to be jitter controlled, the one or morecores selected for jitter control are set by control logic 120 tooperate at a maximum operating frequency that is dependent on the numberof cores in operation (312). In one embodiment, control logic 120 setsthe maximum operating frequency based upon the pre-determined operatingstates 212. In another embodiment, control logic 120 sets the maximumoperating frequency of the jitter controlled cores to the referencefrequency or minimum core operating frequency. Method 300 thenterminates at the end block.

In response to one or more of the cores 104-118 being requested orselected to be disabled in block 302, control logic 120 disables theselected cores from operating at block 304 and determines the coreoperating frequency or turbo states for the enabled cores (306). Controllogic 120 determines if any of the enabled cores are to be jittercontrolled (310). In response to none of the enabled cores beingselected to be jitter controlled, method 300 ends. At block 314, inresponse to one or more of the enabled cores being selected to be jittercontrolled, control logic 120 sets or locks the cores selected forjitter control to operate at a maximum operating frequency or turbostate previously determined at block 306. Method 300 then terminates atthe end block.

Method 300 allows a set of instructions or threads to execute acrossmultiple cores that provide both fast execution times and consistentexecution times (i.e., no jitter). Execution jitter is defined as thedifference in execution time for a given program or thread between thepredicted execution time and the actual execution time at a givenfrequency. With a set of one or more cores 104-118 (e.g., core 4-core 7)fixed to operate at a pre-determined operating frequency, the predictedexecution time and the actual execution time will be the same, resultingin no execution jitter. For example, if the highest clock frequency thata set of instructions or threads executing with consistent executiontimes (no jitter) on multiple cores is 3.5 GHz, method 300 can set orrestrict two or more of the cores 104-118 to operate at 3.5 GHz.

Turning now to FIG. 4 , a flow chart of a method 400 by which cores areenabled is shown. In the discussion of FIG. 4 , reference is also madeto components illustrated in FIG. 1 and FIG. 2 . Method 400 begins atthe start block and proceeds to block 402 where the lookup table 214 isloaded into control logic 120. Lookup table 214 contains an orderedtable of the cores 104-118 ordered by the maximum physical distance orspacing on the chip or die (see, for example, maximum separationdistance between core 0 104 and core 7 118 within processor(s) 102 ofFIG. 1 ). Control logic 120 enables a first one of cores 104-118 (e.g.,core 0 104) for operation in the order defined by lookup table 214(block 404). At block 406, control logic 120 determines if the requestedor selected number of cores have been enabled for operation. Accordingto one aspect of the disclosure, the number of cores selected to beenabled for operation are determined by core configuration parameters210 received from BIOS 134. In response to the selected number of coresbeing enabled, method 400 ends. In response to the selected number ofcores not being enabled, method 400 returns to block 404 where controllogic 120 enables the next core for turbo state operation in the orderdefined by lookup table 214.

FIG. 5 illustrates a flow chart of a method 500 for generating anordered lookup table 214. In the discussion of FIG. 5 , reference isalso made to components illustrated in FIG. 1 and FIG. 2 . Method 500begins at the start block and proceeds to block 502 where one of thecores 104-118 is selected by control logic 120. The selected core isplaced into the lookup table 214 (block 504). At decision block 506,control logic 120 determines if all of the required cores 104-118 havebeen placed into the lookup table 214. In response to all of the coresbeing placed into the lookup table 214, method 500 terminates. Inresponse to there being other cores remaining to be placed into thelookup table 214, control logic 120 selects (at block 508) the next corewith maximum physical spacing distance from the previously selectedcore(s) in the processor (e.g., processor(s) 102, FIG. 1 ), and controllogic 120 places the selected next core into the lookup table 214 (block504). According to one aspect, the next core with maximum physicalspacing distance is selected from among the other non-selected cores(i.e., cores that are not yet placed in the lookup table).

Referring to FIG. 6 , one embodiment of an ordered lookup table 214presenting an increasing number of enabled cores and the correspondingenabled cores (at maximum physical spacing distance) generated by method500 of FIG. 5 is shown. Ordered lookup table 214 is based on the coreswith maximum physical spacing from each other. In the discussion of FIG.6 , reference is also made to components illustrated in FIG. 1 and FIG.2 . Lookup table 214 includes a first column, number of enabled cores602, indicating the different number of cores than can be enabled, and asecond column, enabled core(s) 604, identifying the specific core(s)that is enabled as the number of cores that are enabled increases. Forexample, if one core is to be enabled for operation at a frequencyhigher than the regular or minimum core operating frequency, then theonly core enabled can be core 0 104. If three cores are to be enabledfor operation at a frequency higher than the default or minimum coreoperating frequency, then the cores enabled are the cores with themaximum separation distance beginning with core 0 104 (e.g., core 0 104,core 7 118 and core 1 106 in FIG. 1 ). If five cores are to be enabledfor operation at a frequency higher than the regular or minimum coreoperating frequency, then the cores and sequence of cores that areenabled within processor 102 of FIG. 1 are core 0 104, core 7 118, core1 106, core 6 116, and core 3 110.

In the above described flow chart, one or more of the methods may beembodied in a computer readable medium containing computer readable codesuch that a series of functional processes are performed when thecomputer readable code is executed on a computing device. In someimplementations, certain steps of the methods are combined, performedsimultaneously or in a different order, or perhaps omitted, withoutdeviating from the scope of the disclosure. Thus, while the methodblocks are described and illustrated in a particular sequence, use of aspecific sequence of functional processes represented by the blocks isnot meant to imply any limitations on the disclosure. Changes may bemade with regards to the sequence of processes without departing fromthe scope of the present disclosure. Use of a particular sequence istherefore, not to be taken in a limiting sense, and the scope of thepresent disclosure is defined only by the appended claims.

With the above described systems, computer program products and methods,aspects of the disclosure provide the functionality of reducingexecution jitter in multi-core processors within an information handlingsystem and to selectively enabling one or more processor cores tooperate at a pre-determined frequency.

Aspects of the present disclosure are described above with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems) and computer program products according to embodiments of thedisclosure. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer program instructions. Computer program code for carrying outoperations for aspects of the present disclosure may be written in anycombination of one or more programming languages, including an objectoriented programming language, without limitation. These computerprogram instructions may be provided to a processor of a general purposecomputer, special purpose computer, such as a service processor, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, performs the method forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

As will be further appreciated, the processes in embodiments of thepresent disclosure may be implemented using any combination of software,firmware or hardware. Accordingly, aspects of the present disclosure maytake the form of an entirely hardware embodiment or an embodimentcombining software (including firmware, resident software, microcode,etc.) and hardware aspects that may all generally be referred to hereinas a “circuit,” “module,” or “system.” Furthermore, aspects of thepresent disclosure may take the form of a computer program productembodied in one or more computer readable storage device(s) havingcomputer readable program code embodied thereon. Any combination of oneor more computer readable storage device(s) may be utilized. Thecomputer readable storage device may be, for example, but not limitedto, an electronic, magnetic, optical, electromagnetic, infrared, orsemiconductor system, apparatus, or device, or any suitable combinationof the foregoing. More specific examples (a non-exhaustive list) of thecomputer readable storage device would include the following: anelectrical connection having one or more wires, a portable computerdiskette, a hard disk, a random access memory (RAM), a read-only memory(ROM), an erasable programmable read-only memory (EPROM or Flashmemory), an optical fiber, a portable compact disc read-only memory(CD-ROM), an optical storage device, a magnetic storage device, or anysuitable combination of the foregoing. In the context of this document,a computer readable storage device may be any tangible medium that cancontain, or store a program for use by or in connection with aninstruction execution system, apparatus, or device.

While the disclosure has been described with reference to exemplaryembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the disclosure. Inaddition, many modifications may be made to adapt a particular system,device or component thereof to the teachings of the disclosure withoutdeparting from the essential scope thereof. Therefore, it is intendedthat the disclosure not be limited to the particular embodimentsdisclosed for carrying out this disclosure, but that the disclosure willinclude all embodiments falling within the scope of the appended claims.Moreover, the use of the terms first, second, etc. do not denote anyorder or importance, but rather the terms first, second, etc. are usedto distinguish one element from another.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The description of the present disclosure has been presented forpurposes of illustration and description, but is not intended to beexhaustive or limited to the disclosure in the form disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope of the disclosure. Thedescribed embodiments were chosen and described in order to best explainthe principles of the disclosure and the practical application, and toenable others of ordinary skill in the art to understand the disclosurefor various embodiments with various modifications as are suited to theparticular use contemplated.

What is claimed is:
 1. A computer implemented method of reducingexecution jitter within a processor having a control logic and aplurality of individual cores, the method comprising: receiving at leastone core configuration parameter; determining from the at least one coreconfiguration parameter if a first set of one or more cores is selectedto be disabled from operation; in response to none of the first set ofcores being selected to be disabled,: determining if a second set of oneor more cores is selected to be jitter controlled; and in response tothe second set of cores being selected to be jitter controlled, settingthe second set of cores to a first operating state that reduces jitter;and in response to the first set of cores being selected to bedisabled,: disabling the first set of cores, determining if a third setof one or more enabled cores is selected to be jitter contolled, and;determining a second operating state that reduces jitter for the a thirdset of one or more enabled cores; determining if the third set of coresis selected to be jitter controlled; and in response to the third set ofenabled cores being selected to be jitter controlled, setting the thirdset of enabled cores to the second operating state that reduces jitter.2. The method of claim 1, wherein the at least one core configurationparameter comprises an ordered lookup table of the third set of enabledcores.
 3. The method of claim 1, further comprising: receiving the atleast one core configuration parameter from a basic input output systemstored in memory; and loading the at least one core configurationparameter into the control logic.
 4. The method of claim 1, wherein thefirst operating state comprises a first operating frequency for thesecond set of cores and the second operating state comprises a secondoperating frequency for the third set of cores, and wherein the secondoperating state is based on the number of disabled cores.
 5. The methodof claim 1, wherein the disabled cores do not operate and are selectedto be disabled based on a physical location of each core.
 6. The methodof claim 1, further comprising: determining a third operating state fora fourth set of enabled cores; determining if the fourth set of enabledcores are selected to be jitter controlled; and in response to thefourth set of enabled cores selected to be jitter controlled, settingthe fourth set of enabled cores to the third operating state.
 7. Themethod of claim 1, further comprising: loading, into the control logic,an ordered lookup table of the cores ordered by maximum physical spacingbetween each pair of sequentially enabled cores among a sequence ofenabled cores; enabling operation of a first core in the ordered lookuptable; determining if all of the third set of enabled cores have beenenabled for operation; and in response to all of the third set ofenabled cores not being having been enabled, enabling operation of anext sequential core in the ordered lookup table.
 8. The method of claim1, further comprising: selecting a first core of the plurality of cores;placing the first core in a first position in an ordered lookup table;determining if all of the cores have been placed in the lookup table;and in response to all of the cores not having been placed in the table,selecting a second core with maximum spacing from the other cores thatare not yet selected for the table and placing the selected second corein a next sequential position in the ordered lookup table.
 9. Amulti-core processor, comprising: a plurality of cores in communication;and control logic in communication with the plurality of cores andhaving firmware executing thereon, wherein execution of the firmwareconfigures the control logic to: receive at least one core configurationparameter; determine from the at least one core configuration parameterif a first set of one or more cores are is selected to be disabled fromoperation; in response to none of the first set of cores being selectedto be disabled,; determine if a second set of one or more cores are isselected to be jitter controlled; and in response to the second set ofthe cores being selected to be jitter controlled, set the second set ofcores to a first operating state that reduces jitter; and in response tothe first set of cores being selected to be disabled,; disable the firstset of cores from operation based on a physical location of eachcoreand; determine a second operating state that reduces jitter for athird set of one or more enabled cores; determine if the third set ofenabled cores are is selected to be jitter controlled; and in responseto the third set of enabled cores being selected to be jittercontrolled, set the third set of enabled cores to the second operatingstate that reduces jitter.
 10. The multi-core processor of claim 9,further comprising wherein upon execution of the firmware, the controllogic that receives the at least one core configuration parameter, andwherein the at least one core configuration parameter comprises anordered lookup table of the third set of enabled cores.
 11. Themulti-core processor of claim 9, further comprising logic that whereinupon execution of the firmware, the control logic: receives the at leastone core configuration parameter in a basic input output system memory;and loads the at least one core configuration parameter into the controllogic.
 12. The multi-core processor of claim 9, wherein the firstoperating state comprises a first operating frequency for the second setof cores and the second operating state comprises a second operatingfrequency for the third set of cores, and wherein the second operatingstate is based on the number of disabled cores.
 13. The multi-coreprocessor of claim 9, further comprising logic that wherein uponexecution of the firmware, the control logic: determines a thirdoperating state for a fourth set of enabled cores; determines if thefourth set of enabled cores are selected to be jitter controlled; and inresponse to the fourth set of enabled cores selected to be jittercontrolled, sets the fourth set of enabled cores to the third operatingstate.
 14. The multi-core processor of claim 9, further comprising logicthat wherein upon execution of the firmware, the control logic: loads anordered lookup table of the cores ordered by maximum spacing into thecontrol logic; enables a first core in the ordered lookup table;determines if all of the third set of enabled cores have been enabledfor operation; and in response to all of the third set of enabled coresnot having been enabled, enables a subsequent second core in the orderedlookup table.
 15. The multi-core processor of claim 9, furthercomprising logic that wherein upon execution of the firmware, thecontrol logic: selects a first core of the plurality of cores; placesthe first core in a first position in an ordered lookup table;determines if all of the cores have been placed in the lookup table; andin response to all of the cores not having been placed in the table,selects a second core with maximum spacing from the other cores andplacing places the selected second core in a second position in theordered lookup table.
 16. An information handling system InformationHandling System (IHS), comprising: a processor having a plurality ofcores and a control logic; and a memory coupled to the processor via asystem interconnect, the control logic having firmware executing thereonto reduce execution jitter, wherein execution of the firmware configuresthe control logic to: receive at least one core configuration parameter;determine from the at least one core configuration parameter if a firstset of one or more cores are is selected to be disabled from operation;in response to a determination that none of the first set of cores beingis selected to be disabled,; determine if a second set of one or morecores are is selected to be jitter controlled; and in response to thesecond set of the cores being selected to be jitter controlled, set thesecond set of cores to a first operating state that reduces jitter; inresponse to the first set of cores being selected to be disabled,;disable the first set of cores from operationand; determine a secondoperating state that reduces jitter for a third set of one or moreenabled cores; determine if the third set of enabled cores is selectedto be jitter controlled; and in response to the third set of enabledcores being selected to be jitter controlled, set the third set ofenabled cores to the second operating state that reduces jitter.
 17. Theinformation handling system IHS of claim 16, wherein upon execution ofthe firmware: the control logic further receives the at least one coreconfiguration parameter that includes an ordered lookup table of thethird set of enabled cores; and the first operating state comprises afirst operating frequency for the second set of cores and the secondoperating state comprises a second operating frequency for the third setof cores, and wherein the second operating state is based on the numberof disabled cores.
 18. The information handling system IHS of claim 16,wherein upon execution of the firmware, the control logic: determines athird operating state for a fourth set of enabled cores; determines ifthe fourth set of enabled cores is selected to be jitter controlled; andin response to the fourth set of enabled cores being selected to bejitter controlled, sets the fourth set of enabled cores to the thirdoperating state.
 19. The information handling system IHS of claim 16,wherein upon execution of the firmware, the control logic: loads anordered lookup table of the cores ordered by maximum spacing into thecontrol logic; enables a first core in the ordered lookup table;determines if all of the third set of enabled cores have been enabledfor operation; and in response to all of the third set of cores notbeing having been enabled, enables a subsequent second core in theordered lookup table.
 20. The information handling system IHS of claim16, wherein upon execution of the firmware, the control logic: selects afirst core of the plurality of cores; places the first core in a firstposition in an ordered lookup table; determines if all of the cores havebeen placed in the lookup table; and in response to all of the cores nothaving been placed in the table, selects a second core with maximumspacing from the other cores and placing the selected second core in asecond position in the ordered lookup table.